htw saar Piktogramm QR-encoded URL
Back to Main Page Choose Module Version:
emphasize objectives XML-Code

flag


FPGA Circuit Design with VHDL

(course inactive since 10.11.2017)

Module name (EN):
Name of module in study programme. It should be precise and clear.
FPGA Circuit Design with VHDL
Degree programme:
Study Programme with validity of corresponding study regulations containing this module.
Applied Informatics, Master, ASPO 01.10.2017
Module code: PIM-FPGA
Hours per semester week / Teaching method:
The count of hours per week is a combination of lecture (V for German Vorlesung), exercise (U for Übung), practice (P) oder project (PA). For example a course of the form 2V+2U has 2 hours of lecture and 2 hours of exercise per week.
2SU+2PA (4 hours per week)
ECTS credits:
European Credit Transfer System. Points for successful completion of a course. Each ECTS point represents a workload of 30 hours.
5
Semester: 1
Mandatory course: no
Language of instruction:
German
Assessment:
Project/lecture/presentation

[updated 20.12.2017]
Applicability / Curricular relevance:
All study programs (with year of the version of study regulations) containing the course.

KI753 Computer Science and Communication Systems, Master, ASPO 01.04.2016 , semester 1, optional course, telecommunications-specific, course inactive since 10.11.2017
KIM-FPGA Computer Science and Communication Systems, Master, ASPO 01.10.2017 , semester 1, optional course, telecommunications-specific, course inactive since 10.11.2017
MST.FPG Mechatronics and Sensor Technology, Master, ASPO 01.04.2016 , optional course, course inactive since 10.11.2017
PIM-WI75 Applied Informatics, Master, ASPO 01.10.2011 , semester 1, optional course, informatics specific, course inactive since 10.11.2017
PIM-FPGA Applied Informatics, Master, ASPO 01.10.2017 , semester 1, optional course, informatics specific, course inactive since 10.11.2017
MST.FPG Mechatronics and Sensor Technology, Master, ASPO 01.10.2011 , semester 9, optional course, course inactive since 10.11.2017
Workload:
Workload of student for successfully completing the course. Each ECTS credit represents 30 working hours. These are the combined effort of face-to-face time, post-processing the subject of the lecture, exercises and preparation for the exam.

The total workload is distributed on the semester (01.04.-30.09. during the summer term, 01.10.-31.03. during the winter term).
60 class hours (= 45 clock hours) over a 15-week period.
The total student study time is 150 hours (equivalent to 5 ECTS credits).
There are therefore 105 hours available for class preparation and follow-up work and exam preparation.
Recommended prerequisites (modules):
None.
Recommended as prerequisite for:
Module coordinator:
Prof. Dr.-Ing. Jürgen Schäfer
Lecturer: Prof. Dr.-Ing. Jürgen Schäfer

[updated 10.11.2016]
Learning outcomes:
Students will learn methods for abstracting circuitry problems and become acquainted with the basics of a basic hardware description language.

[updated 20.12.2017]
Module content:
- Structure of a FPGA
- VHDL basics
- The programming environment ´Xilinx ISE Design Suite´
- Projects
  -- Getting started
  -- Reading the status of switches, scanners and angle decoders
  -- Driving a 7-segment display
  -- Driving an LCD display
  -- Connect external components via SPI
  -- Implementing a RS232-UART with transmit and receive FIFO


[updated 20.12.2017]
Teaching methods/Media:
Students will work on their projects independently in small groups. An FPGA development board will be available to each group for this purpose.

[updated 20.12.2017]
Recommended or required reading:
J. Reichardt, B. Schwarz: VHDL-Synthese, Oldenburg
P. P. Chu: RTL Hardware Design Using VHDL, John Wiley & Sons


[updated 20.12.2017]
 
[Sun Apr 28 19:40:33 CEST 2024, CKEY=xfmv, BKEY=pim2, CID=PIM-FPGA, LANGUAGE=en, DATE=28.04.2024]